`timescale 1ns / 1ps

module bcdcounter_tb;

	// Inputs
	reg clk;
	reg en;
    reg r;
	// Outputs
	wire co;
    wire [7:0] q;

	// Instantiate the Unit Under Test (UUT)
	 bcdcounter #(.modulus(0'h23)) uut (
		.clk(clk),
        .r(r), 
		.en(en), 
		.co(co),
        .q(q));

	//clk
   always #50 clk=~clk;
	
	//  clr
	initial 
	 begin
	   clk = 0;r=0;en = 0;
         #(51) r=1;
         #(100)r=0;en=1;
         #(800)
         repeat (40)  begin 
	     #(100*3)  en=1;
	     # 100  en=0; end
         #100 $stop;
     end
      
endmodule

